Achronix Speedster22i Interlaken Manual do Utilizador

Speedster22i Interlaken User Guide UG032 – May 15, 2014 UG032, May 15, 2014

Typical Operation The IIPC can be used in a variety of applications, and provides the user all of the flexibility offered by the Interlaken Protocol.

scheduling function. The user need not be concerned about any of the lower level Interlaken Protocol details. UG032, May 15, 2014

Clocking The IIPC has three major clock domains: 1. LBUS clock Domain • The clk input port is used to clock the protocol processing of the IIPC. T

Figure 3: RX Clock Domains hs_ifper_lane_rxrx_destripingclkserDesIIPC Corehs_ifper_lane_rxserDeshs_ifper_lane_rxserDeshs_ifper_lane_rxserDeshs_i

Figure 4: TX Clock Domains hs_if per_lane_txtx_stripingclktx_serdes_refclkserDesIIPC Corehs_ifper_lane_txserDeshs_ifper_lane_txserDeshs_if per_lane_t

Port List Table 1 shows the port list for the IIPC. More detail on the use of each signal is given in the User Interfaces section. Table 1 – Port D

Name Direction Clock Description corresponding bit of this bus. rx_serdes_resetn[11:0] Input Reset for each RX SerDes lane. The recovered clock

Name Direction Clock Description indicates the channel number of the in-flight packet and is only valid in cycles that rx_enaout is sampled as 1.

Name Direction Clock Description tx_ovfout Output clk Transmit LBUS Overflow. This signal indicates whether the user has violated the back press

Name Direction Clock Description tx_eopin are sampled as 1. When tx_eopin and tx_errin are sampled as 1, the value of tx_mtyin[2:0] is ignored as

Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark and Speedster is a registered tradema

Name Direction Clock Description Words between two Control Words) was shorter than the value specified by ctl_tx_burstshort. This signal is only a

Name Direction Clock Description Definition rev1.2. stat_rx_crc32_err[11:0] Output clk Diagnostic Word CRC32 Error/Invalid. This bus provides ind

Name Direction Clock Description de-skewed. A value of 1 indicates all lanes are aligned and de-skewed. When this signal is a 1, the RX path is al

Name Direction Clock Description expected Meta Frame Synchronization Word across all (active) lanes. This signal can be used to collect the statis

User Interfaces The IIPC handles the intricate details of transporting data over an Interlaken link. The user interface is a simple packet interface d

TX LBUS Interface The synchronous TX Local bus interface accepts packet oriented data of arbitrary length. It accepts data in either packet mode, or s

1, the value of tx_mtyin[2:0] is ignored as if it was 000. The other bits of tx_mtyin are used as usual. Data can be safely written, i.e. tx_enain ass

• It also strongly recommended that the changing of channels be such that the number of bytes between Control Words, whether forced (via tx_bctlin) o

RX LBUS Interface The synchronous RX Local bus interface provides packet oriented data much like the TX Local bus interface accepts. All signals are s

• The user logic must be capable of receiving data when rx_enaout is asserted, and use the Interlaken flow control mechanism to stop the far device (

Table of Contents Copyright Info ... 2 Table of Contents ...

Status/Control Interface The Status/Control interface allows the user to setup the IIPC configuration and to monitor the status of the IIPC directly.

• Four consecutive invalid Meta Frame Synchronization Words were detected in the corresponding lane, or • Three consecutive invalid Scrambler State

This signal is asserted for one clock period each time a CRC24 error is detected. stat_rx_msop_err Packets received with a particular channel address

CRC32 Diagnostics Checking Interlaken implements a CRC32 check for each lane of the interface in order for the user to monitor the health of each lane

Interlaken Status Messaging for the Transmitter The Transmitter is capable of inserting the Status Messaging as described in the Interlaken Protocol i

Transmitter Flow-Control Inputs The IIPC implements the Interlaken in-band flow control mechanism. This mechanism communicates XON/XOFF for different

Register Interface The register interface provides access to control and status registers for the IIPC. These registers can be accessed via the FPG

0x0110 txrlimintv TX Rate Limiter Update Interval Register – R/W Bits 7:0 specify the interval, in Local bus clock cycles, that the token bucket wil

0x014A txstat TX Status Register – R/W Bit 3: Set to a value of 1 if tx_ovfout is asserted on the TX LBUS. Write 1 to clear. Bit 2: Set to a val

0x0210 to 0x022E rxfcstat0-15 RX In-band Flow Control Registers (0-15) - RO Provides the most recent value for in-band flow control for lanes 0-255.

TX Rate Limiting ... 48 Example: Programming the Rate Limit

0x0880 to 0x08AE statistics counters RX CRC32 Error Statistics Registers – RO 0x0880 Bit 15:0 – returns the value contained in bits 15-0 (LSB) of RX C

0x0980 to 0x09AE statistics counters RX Word Boundary Synchronization Error Statistics Registers – RO 0x0980 Bit 15:0 – returns the value contained

0x0A80 to 0x0AAE statistics counters RX Bad Type Error Statistics Registers – RO 0x0A80 Bit 15:0 – returns the value contained in bits 15-0 (LSB) o

0x0B80 to 0x0BAE statistics counters RX Meta Frame Length Error Statistics Registers – RO 0x0B80 Bit 15:0 – returns the value contained in bits 15-

0x0C80 to 0x0CAE statistics counters RX Descrambler Error Statistics Registers – RO 0x0C80 Bit 15:0 – returns the value contained in bits 15-0 (LSB

Description of Features Lane Decommission The IIPC features two different modes of lane decommissioning: 1. Disabling consecutive lanes, and 2. Disa

Disabling a Single Lane Single Transmit Lane To disable one of the lanes in the range between 0 to ctl_tx_last_lane, the parameters ctl_tx_has_bad_lan

Link Level Flow Control The Interlaken Protocol does not restrict the use of the calendar entries to a particular flow control implementation. As such

TX Rate Limiting The IIPC rate limiter can be used to reduce the overall Data Word transmission rate. This is achieved by transmitting Idle Control W

ctl_tx_rlim_intv[11:0] This input specifies how many tokens are to be added to the bucket after each interval. A token is equal to 1 byte. This value

Table of Figures Figure 1: Shows a block diagram of IIPC with SerDes and user logic interface ... 8 Figure 2: IIPC Hierarchy ...

Error Handling The IIPC performs robust checking of all possible error conditions as described in the Interlaken Protocol Definition including the fol

Revision History The following table shows the revision history for this document. Date Version Revisions 4/26/2013 1.0 Initial release 4/28/2014 1.

Introduction Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gbps and beyond. Usi

• Segment-mode and Packet-mode receive format • BurstMax size can be programmed from 64 bytes to 256 bytes in steps of 64 bytes • Support for minim

Design Overview Figure 1 shows a block diagram of the IIPC with SerDes and user logic interfaces implemented in Speedster22i. The right hand side is

Hierarchy The interfaced IIPC and SerDes IP is configured using the Achronix Cad Environment (ACE) Interlaken GUI. The upper-levels of hierarchy are s