Achronix Speedster22i Memory PHY Manual do Utilizador

UG043, April 26, 2014 1 Speedster22i Memory PHY User Guide UG043 – April 26, 2014

10 UG043, April 26, 2014 PHY Structure and Operation Figure 5 below illustrates a high level overview of the DDR PHY structure. It consists of up t

UG043, April 26, 2014 11 PHY – Controller Interfacing through Widebus The DDR PHY in Speedster22i HD devices provides a half-rate interface to the pro

12 UG043, April 26, 2014 Byte Lane Building Blocks As shown in Figure 5, the DDR PHY is made up of up to 9 data byte lanes (for a x72 mode interfa

UG043, April 26, 2014 13 ddr3_dq9_bit/postamble/ddr3_dqs_bit: These are the modules used to transmit and receive dqs pulses to sample the data at dq.

14 UG043, April 26, 2014 TX, RX and OE paths in Data Bits This section highlights the pieces of the TX, RX and OE circuitry that make up each of th

UG043, April 26, 2014 15 Transmit path: If half-rate (or quarter-rate with the widebus wrapper) is used in the fabric, four-wide data is provided from

16 UG043, April 26, 2014 DQS Clocking and Circuitry The circuitry in Figure 9 below shows how the DQS signal coming from or going to dqsn/dqsp is t

UG043, April 26, 2014 17 DLL Specs and Operation The DLL IP block in the Speedster22i HD1000 is wide range DLL with 1 Master DLL (MDLL) and 12 Slave D

18 UG043, April 26, 2014 The MDLL uses a regulated supply generated by a high performance on-board regulator to achieve the best possible performan

UG043, April 26, 2014 19 Mux Output Option Ph0 Ph1 9 180 202.5 10 202.5 225 11 225 247.5 12 247.5 270 13 270 292.5 14 292.5 315 15 315 337.5 16 337.5

2 UG043, April 26, 2014 Copyright Info Copyright © 2013 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark

20 UG043, April 26, 2014 Revision History The following table shows the revision history for this document. Date Version Revisions 04/26/2014 1.0 I

UG043, April 26, 2014 3 Table of Contents Copyright Info ...

4 UG043, April 26, 2014 Overview Speedster22i HD devices have a flexible and feature rich PHY with building blocks to implement a PHY capable of in

UG043, April 26, 2014 5 As stated above, there are 12 IOs in a byte-lane. A group of byte-lanes make up an IO bank and 3 IO banks build an IO cluster

6 UG043, April 26, 2014 Core FabricWN IO ClusterWN Hard DDR3 ControllerWC IO ClusterWC Hard DDR3 ControllerWS IO ClusterWS Hard DDR3 ControllerEN H

UG043, April 26, 2014 7 DDR PHY Organization and Interfaces Figure 4 provides a block diagram view of how the DDR PHY is organized, and how it interfa

8 UG043, April 26, 2014 Table 1: DDR PHY – Hard/Soft Controller Interface Port List Signal Name Bus Width Direction Description clk 1 Input User re

UG043, April 26, 2014 9 Signal Name Bus Width Direction Description phy_ctrli_dq/dqs_croe{a,b} N/8 Input Data a and b termination resistance enable si