Achronix Speedster22i Memory PHY Manual do Utilizador descarregar pdf (Página 3)

UG043, April 26, 2014

Table of Contents

Table of Contents .............................................................................................. 3

Overview ............................................................................................................ 4

DDR PHY ............................................................................................................ 7

Organization and Interfaces ................................................................................................... 7

PHY Structure and Operation .............................................................................................. 10

PHY – Controller Interfacing through Widebus .................................................................... 11

Byte Lane Building Blocks.................................................................................................... 12

TX, RX and OE paths in Data Bits ....................................................................................... 14

DQS Clocking and Circuitry ................................................................................................. 16

DLL Specs and Operation ............................................................................... 17

Revision History .............................................................................................. 20

1 2 3 4 5 6 7 8 ... 19 20

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