Achronix Speedster22i 10G/40G/100G Ethernet Manual do Utilizador Página 5
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UG029, September 6, 2013
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Transmit Timestamping ....................................................................................................... 58
MAC & PCS Configuration Registers ............................................................. 59
MAC & PCS Register Overview ........................................................................................... 59
Channelized MAC Registers ................................................................................................ 61
COMMAND_CONFIG Register Bit Definitions .............................................................................. 67
STATUS Register Bit Definitions .................................................................................................. 70
10G MAC SGMII PCS Register Map ................................................................................... 71
1000Base-X / SGMII PCS .................................................................................................... 71
1000Base-X/SGMII PCS Registers Description ........................................................................... 73
Global Registers .................................................................................................................. 77
Core Configuration Registers ....................................................................................................... 77
VLAN Tag Configuration Registers .............................................................................................. 78
Channelized PCS Registers................................................................................................. 79
Auto-Negotiation Registers .................................................................................................. 87
Control Register Bits (KXAN_CONTROL) .................................................................................... 89
Status Register Bits (KXAN_STATUS) ......................................................................................... 89
Ability Register Bits (KXAN_ABILITY / KXAN_REM_ABILITY) ..................................................... 90
Next page Ability Register Bits (AN_XNP / LP_AN_XNP) ............................................................ 91
PMA Registers ................................................................................................. 93
PMA State Control ............................................................................................................... 93
Memory Bus (Membus) Interface ................................................................................................. 93
Memory Address Decoding .......................................................................................................... 93
PMA Receive Equalization Registers ................................................................................... 93
TX/RX Lane Receive Equalization Registers................................................................................ 94
Common/Synth Lane Receive Equalization Registers .................................................................. 96
PMA Transmit Control Registers .......................................................................................... 96
TX/RX Lane Transmit Control Registers ...................................................................................... 96
Common/Synth Lane Transmit Control Registers ........................................................................ 97
PMA Adaptive Equalizer Registers ...................................................................................... 98
TX/RX Lane Adaptive Equalizer Registers ................................................................................... 98
Common/Synth Lane Adaptive Equalizer Registers ..................................................................... 99
Statistics Data Registers .............................................................................. 102
Overview ............................................................................................................................ 102
IEEE 802.3 Management Package .................................................................................... 102
IETF Management Information Base (MIB, MIB-II) Objects ............................................... 102
IETF Remote Network Monitoring ...................................................................................... 102
Receive Statistics Vector ................................................................................................... 103
Transmit Statistics Vector .................................................................................................. 105
- Speedster22i 10/40/100 1
- Gigabit Ethernet User Guide 1
- Copyright Info 2
- Table of Contents 3
- Table of Figures 7
- Overview 8
- Functional Description 10
- Interface Signal List 12
- Global Signals 13
- Receive FIFO Interface 13
- Transmit FIFO Interface 15
- PMA TX/RX Interface 16
- Signal Name 17
- Serial Bus Interface 18
- SerDes (off-chip) Interface 19
- Transmitted Frame Status 19
- Timestamp Timer 19
- MAC/PCS Status Indications 20
- Implementation with ACE 21
- Simulation 24
- .vp or .ve file extenstion 25
- .vma file extenstion 25
- Clock Distribution 26
- Reset Considerations 28
- Fabric FIFO Interface 29
- Credit Handling 32
- Data Structure 33
- Valid Bytes 34
- Byte Number 36
- Frame Status 42
- FIFO Thresholds 43
- FIFO nearly full 44
- FIFO has at least 44
- FIFO is full 44
- Flow Control Interface 45
- Transmit Pause/PFC Operation 47
- Receive Pause/PFC Operation 47
- Write Operation 50
- PMA Management Interface 51
- Power State Sequencing 53
- Auto-Negotiation 54
- Function 55
- Related 55
- Registers 55
- IEEE 1588 Timestamping 58
- Channelized MAC Registers 61
- Transmitted 64
- Bit Name 70
- 1000Base-X / SGMII PCS 71
- Global Registers 77
- Channelized PCS Registers 79
- Auto-Negotiation Registers 87
- PMA Registers 93
- 1A[7:4] 95
- 1B[3:0] 95
- 1B[6:4] 95
- 1C[7:3] 95
- +1 is 4’h9 96
- 51[3:2] 97
- 53[2:2] 97
- 53[3:3] 97
- 8[6:6] 99
- 21[5:1] 99
- 23[5:1] 99
- 25[2:0] 99
- UG029, September 6, 2013 101
- Statistics Data Registers 102
- Receive Statistics Vector 103
- Description 104
- Transmit Statistics Vector 105
- References 107
- Revision History 108
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