Achronix Speedster22i HD1000 Development Kit User Guide Manual do Utilizador descarregar pdf (Página 45)

UG034, July 1, 2014

Signal Name

Pin on HD1000 (U33)

Pin on MT44K32M18RB

(U31)

(U36)

RLD_QK1

AA3

RLD_QK1_N

AA4

RLD_QK2

RLD_QK2_N

V10

RLD_QK3

RLD_QK3_N

RLD_DK0

P11

RLD_DK0_N

P12

RLD_DK1

RLD_DK1_N

RLD_DM2

RLD_DM3

RLD_QK4

RLD_QK4_N

RLD_QK5

RLD_QK5_N

RLD_QK6

RLD_QK6_N

RLD_QK7

RLD_QK7_N

P10

RLD_DK2

RLD_DK2_N

RLD_DK3

RLD_DK3_N

Note: TDI, TDO, TMS and TCK (pins N10, N4, N12, and N2) are jumpered using J517 and J516 to

the device (U31) pins and J544 and J545 to the device (U36) pins.

QDR2+ Device (72 Mb)

You can use the Cypress Semiconductor CY7C2565XV18, 72 Mb QDR2+ memory device

soldered on the board. The HD1000 drives the memory signals using dedicated GPIOs.

Although you may repurpose these IO pins, Bank East-North (Byte 0 – 12), on your designs,

you must maintain the allocation shown in Table 15 to use the device provided on the board.

Note: Do not reallocate these Ios on the ACX-BRD-HD1000-100G development board. This could

lead to unexpected behavior.

Note: Table 15 shows only the logical connection for application development. Relevant voltage levels

are driven on the board by additional circuitry.

Table 15: ACX-BRD-HD1000-100G Memory Interfaces – CY7C2565XV18

Signal Name

Pin on HD1000 (U33)

Pin on CY7C2565XV18 (U22)

QDR2_Q0

AW42

P11

QDR2_Q1

AY43

M10

QDR2_Q2

BA42

L11

QDR2_Q3

BB43

K11

QDR2_Q4

BC42

J10

QDR2_Q5

BB41

F11

QDR2_Q6

AW40

E11

1 2 ... 40 41 42 43 44 45 46 47 48 49 50 ... 68 69

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