Achronix Speedster22i Clock and Reset Networks Manual do Utilizador

UG027, May 21, 2014 1 Speedster22i Clock and Reset Networks User Guide UG027 – May 21, 2014

10 UG027, May 21, 2014 Core Clock Network Components Figure 3 provides block level highlights of the different core clock network components on the

UG027, May 21, 2014 11 Table 3: Snapshot of HD1000 52.5mm package spreadsheet to show clock buffers Port_Name DIFF-PAIR USE BANK PURPOSE CLK/RST USE

12 UG027, May 21, 2014 The PLL contains the following major blocks: reference clock divider, feedback divider, sigma-delta modulator, phase rotator

UG027, May 21, 2014 13 The PLL IP comes with a built-in LDO and a Band Gap reference circuit. The LDO takes external analog voltage (PA_VDD, 1.5V to 1

14 UG027, May 21, 2014 On the other hand, the “Advanced PLL” gives users much more flexibility in setting up the individual PLL parameters, setting

UG027, May 21, 2014 15 into the clock hub. Figure 6 below provides a detailed view of the internals of the clock mux located at the top center of the

16 UG027, May 21, 2014 Clock Hub32From Clock Mux Top32From Clock Mux Bottom16From data interconnect in fabric80 to 48 Crossbar484848484848484848121

UG027, May 21, 2014 17 12RLBsRLBsRLBsCRMURLBsRLBsRLBsBRAMsBRAMsBRAMsBRAMsBRAMsBRAMsRLBsRLBsRLBsRLBsRLBsRLBsMULTsMULTsMULTsMULTsMULTsMULTsRLBsRLBsRLBsR

18 UG027, May 21, 2014 CRMU32 to 8 CrossbarAdditional Control Logic32 to 8 CrossbarAdditional Control LogicClk Div & GatingClk Div & Gating

UG027, May 21, 2014 19 Junctions Data-to-Clock Junctions There are multiple junction-points in the fabric where a data-interconnect signal can drive a

2 UG027, May 21, 2014 Copyright Info Copyright © 2014 Achronix Semiconductor Corporation. All rights reserved. Achronix is a trademark an

20 UG027, May 21, 2014 Byte-Lane Clocks For source synchronous transfers, where data and clock are both sent from the IO ring to the core, using on

UG027, May 21, 2014 21 Boundary Clock Network The boundary clock network is an architectural feature available in Speedster22iHD FPGAs to help improve

22 UG027, May 21, 2014  Global Clock Mux (GCM)  Quadrant Clock Mux (QCM)  Region Clock Mux (RCM)  Byte-Lane Clock Mux (BCM) The global boun

UG027, May 21, 2014 23 Clock Setting and Reporting Much of the decision making and optimization for clock selection is automatically done by the ACE t

24 UG027, May 21, 2014 Reset Network This chapter examines the reset network in a little more detail and provides information on the different netw

UG027, May 21, 2014 25 and (b) even if it did the user wouldn’t be able to do anything to fix timing problems in the I/O ring. For resets going into t

26 UG027, May 21, 2014 Port_Name DIFF-PAIR USE BANK PURPOSE CLK/RST USE pad0_clk_bank_se P C CB2 USER CLK RST pad0_clk_bank_sw P C CB1 U

UG027, May 21, 2014 27 FPGA CoreReset sourceReset sourceReset sourceReset source8 bit8 bit8 bit8 bit8 bit8 bit8 bit8 bitPLogic BlockP P PP PPP P PP PP

28 UG027, May 21, 2014 Revision History The following table shows the revision history for this document. Date Version Revisions 04/05/2013 1.0 Ini

UG027, May 21, 2014 3 Table of Contents Copyright Info ...

4 UG027, May 21, 2014 Introduction Clock and Reset Networks Overview Speedster22iHD FPGAs have two hierarchical clock networks: a core clock networ

UG027, May 21, 2014 5 Reset Resource Counts The following table lists the reset resources available on Speedster22iHD FPGAs. Table 2: Reset Resource C

6 UG027, May 21, 2014 Clock Sources As mentioned earlier, the clock sources are Clock Generators (CGs) and recovered SerDes input clocks. There are

UG027, May 21, 2014 7 Core Clock Network This chapter focuses solely on the core clock network, illustrating the global and direct core clock network

8 UG027, May 21, 2014 GPIO GPIOSerDesSerDesGCGGCGGCGGCG Figure 1: Global Core Clock Network Direct Core Clock Network The direct core clock netwo

UG027, May 21, 2014 9 GPIO GPIOSerDesSerDesGCGGCGGCGGCG Figure 2: Direct Core Clock Network