Achronix Speedster22i Clock and Reset Networks Manual do Utilizador Página 19
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UG027, May 21, 2014
19
Junctions
Data-to-Clock Junctions
There are multiple junction-points in the fabric where a data-interconnect signal can drive a
clock network signal:
a. Clock Hub (16 data inputs; already discussed above),
b. CRMU (4 data inputs per region; already discussed above),
c. RLB input (any Logic Cluster clock can be driven by a selected data signal),
d. Selected BRAM, LRAM, or Multiplier input.
Based on the fanout and other requirements of the clock signal that is generated in the data
interconnect portion of the programmable logic fabric, an appropriate junction point would
be selected by ACE.
Clock-to-Data Junctions
Switching elements can allow some LUT inputs, BRAM inputs, LRAM inputs, and BMAC
inputs to be driven by a signal outputted by the CRMU. In particular, this would allow
certain functions that may have high fanout like register resets and clock enables to be driven
by signals from the CRMU.
- Speedster22i Clock and 1
- Reset Networks 1
- User Guide 1
- Copyright Info 2
- Table of Contents 3
- Introduction 4
- Reset Resource Counts 5
- Clock Sources 6
- Reset Sources 6
- Core Clock Network 7
- Direct Core Clock Network 8
- Clock Generator (CG) 10
- Phase Locked Loop (PLL) 11
- 12 UG027, May 21, 2014 12
- UG027, May 21, 2014 13
- Clock Mux 14
- Clock Hub 15
- Clock Region 16
- Clk Div & 18
- Junctions 19
- West-North (WN) IO Cluster 20
- Boundary Clock Network 21
- 22 UG027, May 21, 2014 22
- Clock Setting and Reporting 23
- FPGA Core 24
- Reset Distribution 26
- Revision History 28
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