Achronix ACE Version 5.0 Manual do Utilizador descarregar pdf (Página 38)

100

101

Editors Chapter 3. Concepts

Output Register

Clock Enable Priority Y

The Clock Enable Priority deﬁnes the priority

of the outregceb clock enable input relative

to the rstregb reset input during an assertion

of the rstregb signal on the output register of

Port B. The value rstreg allows the Port B

output register to be set/reset at the next

active edge of the Port B clock without

requiring a speciﬁc value on the outregceb

output register clock enable input. The value

regce requires that the outregceb output

output register set/reset operation to occur at

the next active edge of the Port B clock.

Output Register Reset

Active-High

When this is enabled, the output register has

an active-high synchronous reset. Otherwise,

the output register reset will be active-low.

Total Memory Size Port A Address Depth x Port A Data Width

Number of BRAMs Used The total number of BRAM instances which

will be used to create a BRAM wrapper of the

conﬁgured width(s) and depth(s).

UG001 Rev. 5.0 - 5th December 2012 http://www.achronix.com 26

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 388 389

Comentários a estes Manuais

Sem comentários

Achronix ACE Version 5.0 Manual do Utilizador Página 38

Comentários a estes Manuais

Manuais e produtos relacionados com Hardware de computador Achronix ACE Version 5.0