Achronix Speedster22i SerDes Manual do Utilizador Página 108
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Receiver
Table 26: DC and AC Switching Characteristics
Parameter
Description
Min
Typ
Max
Unit
V
RX-DIFF-PKPK
Differential Input Peak to Peak Voltage for
AC coupnling
-
2000
mV
diffp-
p
V
RX-CM-DC
Receiver Input DC Common Mode Voltage
0
mV
diff-
pkpk
V
RX-CM-AC
Receiver Input AC Common Mode Voltage
-150
150
mV
diff-
pkpk
V
RX-SENS
Receiver Input Voltage Sensitivity
30
mV
diff-
pkpk
FPPM-OFFSET
Frequency tolerance
-
5350
650 350 PPM
V
RX
Common mode AC return loss (standard
specific)
2
12 dB
V
RX
Power down DC input impedance
200
k
Ω
V
RX
Input common mode frequency
2
200
MHz
JTOL (TJ)
Total Jitter Tolerance
0.65
0.95
UIpp
JTOL (RJ)
Random Jitter Tolerance
0.15
0.30
UIpp
JTOL (DJ)
Deterministic Jitter Tolerance
0.30
0.68
UIpp
T
RX-DDJ
Receive Input Signal Data Dependant Jitter
(Inter-Symbol Interference).
1
UI
pkpk
T
RX-RJ
Receive Input Random Jitter
0.3
UI
pkpk
T
RX-PJ
Receive Input Period Jitter (at high
frequency)
0.1
UI
pkpk
T
RX-TJ
Receive Input Total Jitter (DDJ + RJ + PJ).
1
UI
pkpk
N
GPLL
F3dB cutoff frequency for the 1
st
Order High-
Pass Jitter Measurement Filter.
Defined as the ratio of the F3DB cutoff
frequency, to the data rate
1667
F
BAUD
/
FGPLL
V
ADC-RES
ADC Sampling Voltage Resolution per LSB
8
mV
diff
VADC-RANGE
ADC Full-scale Differential Peak-Peak
Voltage Range defined at the Input Pins of
the SerDes
700
mV
diff
-
pkpk
VADC-DNL
ADC Sampling Voltage Differential Non-
Linearity (DNL)
3 mVdiff
T
SAMPLE
ADC Real Time Sampling Rate
2
8
2
UI
T
ADC-RES
ADC Effective Sub-Sampling Rate
1/32
UI
T
ADC-RANGE
Total Time-Domain Sampling Range
1
2
8
UI
TADC-DNL
Time Domain Sampling Differential Non-
Linearity (DNL)
1/32 UI
Z
RL-DIFF-DC
Receiver Differential DC Return Loss
-18
dB
ZRL-DIFF-NYQ
Receiver Differential Return Loss at Nyquist
Frequency (F
BAUD
/2)
-6 dB
Z
RL-CM-DC
Receiver Common-Mode DC Return Loss
-12
dB
108 UG028, July 1, 2014
- Speedster22i SerDes 1
- User Guide 1
- Table of Contents 2
- 4 UG028, July 1, 2014 4
- List of Figures 5
- List of Tables 6
- Overview 7
- Major standards supported 9
- 10 UG028, July 1, 2014 10
- SerDes Placement 11
- SerDes Architecture Overview 12
- 1. Common 13
- 3. Digital PMA (DPMA) 14
- PCS Self Test Logic 16
- 18 UG028, July 1, 2014 18
- Interface Encapsulation 20
- 8b/10b Encoder 20
- Running Disparity 20
- 22 UG028, July 1, 2014 22
- Polarity Bit Reversal (PBR) 23
- Symbol Alignment 23
- Modes of Operation 24
- Manual Mode: 24
- Bit Slip Mode: 24
- Automatic Mode: 24
- Deskew FIFO 25
- Functional Description 26
- Auto Mode: 26
- Symbol slip mode: 27
- 28 UG028, July 1, 2014 28
- EFIFO Operation 29
- 30 UG028, July 1, 2014 30
- 8b/10b Decoder 31
- Bit Slider 31
- PCS Self Test Checker 32
- PCS Interface 33
- PIPE Interface 34
- Clocking 36
- Debug and Test 38
- PMA loopback modes: 39
- PCS loopback modes: 39
- PMA Test Pattern Generator 40
- PMA Test Pattern Checker 40
- PCS Test Pattern Generator 40
- PRBS Generator 40
- PCS Test Pattern Checker 41
- Latency 42
- 44 UG028, July 1, 2014 44
- Configurations Supported 45
- 46 UG028, July 1, 2014 46
- 48 UG028, July 1, 2014 48
- Single-Lane Serdes Wrapper 50
- 52 UG028, July 1, 2014 52
- Overview Section: 53
- Entry field 54
- Purpose 54
- Available Options 54
- Choice made 54
- 56 UG028, July 1, 2014 56
- Section on PMA Settings: 57
- 58 UG028, July 1, 2014 58
- RX PMA Equalization 59
- RX PMA PLL 60
- TX PMA Driver 62
- TX PMA PLL 62
- Section on PCS Settings: 63
- RX PCS Settings 64
- RX PCS Symbol Alignment 66
- TX PCS Settings 68
- 70 UG028, July 1, 2014 70
- Files Generated by ACE-GUI 71
- Design and Wrapper Files 72
- Sequence 74
- 76 UG028, July 1, 2014 76
- Placement of SerDes 77
- Timing Constraints 78
- Design Guidelines 80
- Figure 37: Clock Region View 82
- 84 UG028, July 1, 2014 84
- Wide Bus 86
- Design Tips 87
- 88 UG028, July 1, 2014 88
- 90 UG028, July 1, 2014 90
- 92 UG028, July 1, 2014 92
- Design Bypassing PCS: 93
- Modification – 1 (ACE GUI): 94
- 96 UG028, July 1, 2014 96
- ACX_SERDES_SBUS_IF Module 99
- General signals: 100
- SerDes signals: 100
- Parallel Interface signals: 100
- UG028, July 1, 2014 101
- Pass-through signals: 102
- Loopback Modes 102
- SerDes signals 102
- Control signals 102
- SerDes Registers 103
- Electrical Specifications 104
- Transmitter 105
- 106 UG028, July 1, 2014 106
- Receiver 108
- Eye Diagram 110
- Reference Clock 112
- Revision History 113
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