Achronix Speedster22i SerDes Manual do Utilizador Página 42

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Latency
This section presents the worst case latency for PMA and PCS blocks.
PMA Latency
The following equation calculates the worst-case latency for the Tx-datapth assuming the
case of first word in and last bit out:


= _ + 2.5 _  +
(
_ 1
)
 + 500,
where analog latency is explained below and 500 ps accounts for internal analog delay and
digital clock newtowrk latency.
The worst-case latency for the Rx-datapath can be calculated by the following equation
considering the case of first bit in and first word out:

= 5.5  + 2.5 _  +
(
_ 1
)
 + 500 ,
where 500 ps accounts for internal analog delay and digital clock newtowrk latency.
The analog latency is a function of the databus-width as well and can be estimated using
Table 8: Analog latency as a function of databus widthbelow.
Table 8: Analog latency as a function of databus width
# Databus Width Analog Latency
1.
8-bit
2.
10-bit
3.
16-bit
4.
20-bit
As an example, for 20-bit databus width, the worst case latency for Tx and Rx datapath can
be estimated as follows:


= 43 + 50 + 19 + 500 = 112 + 500, and

= 5.5 + 50 + 19 + 500 = 73.5 + 500
Worst case values are presented in “Figure 20 Worst-case latency across PMA and PCS (in
terms of clock-cycles)”.
PCS Latency
There are two modes of using PCS in Achronix SerDes:
1. PCS Enabled: All or selected PCS blocks can be enabled. Each block will introduce it’s
own latency in datapath. Even when selected blocks are disabled in this mode, data
(transmit and receive) will travel through the PCS components while bypassing them, as
shown in “Figure 6: - PCS Transmitter Block Overview”.
2. PCS Disabled: In this case, all PCS blocks are disabled. This mode introduces a latency of
2 clock-cycles.
42 UG028, July 1, 2014
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