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Reference Clock
The electrical specifications for the reference clock are summarized in the following tables
Table 29: Reference Clock Electrical Speficiations
Parameter
Description
Min
Typical
Max
Unit
FREF
Reference clock operating frequency
range
50 250 MHz
TREF
Reference clock operating frequency
range
4 20 ns
T
REF-DUTY
Duty Cycle
40
50
60
%
T
REF-RISE/FALL
Rise and falling edge rate
0.2
T
REF
T
REF-SINGLEEND-
SKEW
Skew between REFCLKP and REFCLKM 10 ps
T
REF-PPM-ERROR
Reference Clock Frequency Error
-5350
+350
ppm
ZREF-SINGLEEND-DC
Reference Clock Input Impedance –
Terminated Mode
40 50 60
Ω
ZREF-DIFF-DC
Reference Clock Input Impedance – High
Impedance Mode
>200k
Ω
VREF-DIFF
Input Differential Voltage - PCIe
0.15
V
Input Differential Voltage - LVDS
0.25
0.4
V
Input Differential Voltage - LVPECL
0.525
0.95
V
VREF-CM
Input Common Mode Voltage - PCIe
0.25
0.55
V
Input Common Mode Voltage - LVDS
1
1.4
V
Input Common Mode Voltage - LVPECL
1.84
2.1
V
TREF-RMS-MAX
Total Integrated RMS Phase Noise for the
band of frequency ranging from 12kHz to
20MHz
0.7 psRMS
Jitter Specification
Table 30: Reference Clock Jitter Specification
Reference Clock Parameter
Typ
Max
Unit
Suggested RMS phase jitter at 333.3 MHz (12KHz to 20
MHz)
0.8 400 ps rms
Suggested cycle to cycle jitter at 333.3 MHz
51
ps p-p
SATA/SAS: cycle to cycle jitter 112
ps p-
p
SATA/SAS: deterministic jitter
40
ps p-p
FC: cycle-to-cycle jitter RMS
6
ps p-p
FC: deterministic jitter
5
ps p-p
PCI-Express Gen1: cycle to cycle jitter
150
ps p-p
PCI-Express Gen2: 10KHz – 1.5 MHz bandwidth
7.5
ps rms
PCI-Express Gen2: 1.5MHz – 2.5GHz bandwidth
4.0
ps rms
XFI: RMS random jitter (up to 100MHz)
10
ps rms
112 UG028, July 1, 2014
- Speedster22i SerDes 1
- User Guide 1
- Table of Contents 2
- 4 UG028, July 1, 2014 4
- List of Figures 5
- List of Tables 6
- Overview 7
- Major standards supported 9
- 10 UG028, July 1, 2014 10
- SerDes Placement 11
- SerDes Architecture Overview 12
- 1. Common 13
- 3. Digital PMA (DPMA) 14
- PCS Self Test Logic 16
- 18 UG028, July 1, 2014 18
- Interface Encapsulation 20
- 8b/10b Encoder 20
- Running Disparity 20
- 22 UG028, July 1, 2014 22
- Polarity Bit Reversal (PBR) 23
- Symbol Alignment 23
- Modes of Operation 24
- Manual Mode: 24
- Bit Slip Mode: 24
- Automatic Mode: 24
- Deskew FIFO 25
- Functional Description 26
- Auto Mode: 26
- Symbol slip mode: 27
- 28 UG028, July 1, 2014 28
- EFIFO Operation 29
- 30 UG028, July 1, 2014 30
- 8b/10b Decoder 31
- Bit Slider 31
- PCS Self Test Checker 32
- PCS Interface 33
- PIPE Interface 34
- Clocking 36
- Debug and Test 38
- PMA loopback modes: 39
- PCS loopback modes: 39
- PMA Test Pattern Generator 40
- PMA Test Pattern Checker 40
- PCS Test Pattern Generator 40
- PRBS Generator 40
- PCS Test Pattern Checker 41
- Latency 42
- 44 UG028, July 1, 2014 44
- Configurations Supported 45
- 46 UG028, July 1, 2014 46
- 48 UG028, July 1, 2014 48
- Single-Lane Serdes Wrapper 50
- 52 UG028, July 1, 2014 52
- Overview Section: 53
- Entry field 54
- Purpose 54
- Available Options 54
- Choice made 54
- 56 UG028, July 1, 2014 56
- Section on PMA Settings: 57
- 58 UG028, July 1, 2014 58
- RX PMA Equalization 59
- RX PMA PLL 60
- TX PMA Driver 62
- TX PMA PLL 62
- Section on PCS Settings: 63
- RX PCS Settings 64
- RX PCS Symbol Alignment 66
- TX PCS Settings 68
- 70 UG028, July 1, 2014 70
- Files Generated by ACE-GUI 71
- Design and Wrapper Files 72
- Sequence 74
- 76 UG028, July 1, 2014 76
- Placement of SerDes 77
- Timing Constraints 78
- Design Guidelines 80
- Figure 37: Clock Region View 82
- 84 UG028, July 1, 2014 84
- Wide Bus 86
- Design Tips 87
- 88 UG028, July 1, 2014 88
- 90 UG028, July 1, 2014 90
- 92 UG028, July 1, 2014 92
- Design Bypassing PCS: 93
- Modification – 1 (ACE GUI): 94
- 96 UG028, July 1, 2014 96
- ACX_SERDES_SBUS_IF Module 99
- General signals: 100
- SerDes signals: 100
- Parallel Interface signals: 100
- UG028, July 1, 2014 101
- Pass-through signals: 102
- Loopback Modes 102
- SerDes signals 102
- Control signals 102
- SerDes Registers 103
- Electrical Specifications 104
- Transmitter 105
- 106 UG028, July 1, 2014 106
- Receiver 108
- Eye Diagram 110
- Reference Clock 112
- Revision History 113
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