Achronix Speedster22i SerDes Manual do Utilizador descarregar pdf (Página 35)

The 128b/130b encoder is disabled on power up, and enabled when the rate bits coming from

the MAC are configured to 2’b10. The PCS layer support for PCIe gen3 also includes glue

logic to switch the PMA data width to 16-bit mode and programming final rate bits for PCIe

gen3 operation. “Table 5: PIPE Interface Paramaters” shows various supported combinations

of clocking speeds and data-widths.

Table 5: PIPE Interface Paramaters

PCIe Mode

PCLK

PMA Data Width

2.5 Gbps Gen1

250 Mhz

10 bits

2.5 Gbps Gen1

125 Mhz

20 bits

5.0 Gbps Gen2

500 Mhz

10 bits

5.0 Gbps Gen2

250 Mhz

20 bits

8.0 Gbps Gen3

500 Mhz

16 bits

UG028, July 1, 2014

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Speedster22i SerDes 1
User Guide 1
Table of Contents 2
4 UG028, July 1, 2014 4
List of Figures 5
List of Tables 6
Overview 7
Major standards supported 9
10 UG028, July 1, 2014 10
SerDes Placement 11
SerDes Architecture Overview 12
1. Common 13
3. Digital PMA (DPMA) 14
PCS Self Test Logic 16
18 UG028, July 1, 2014 18
Interface Encapsulation 20
8b/10b Encoder 20
Running Disparity 20
22 UG028, July 1, 2014 22
Polarity Bit Reversal (PBR) 23
Symbol Alignment 23
Modes of Operation 24
Manual Mode: 24
Bit Slip Mode: 24
Automatic Mode: 24
Deskew FIFO 25
Functional Description 26
Auto Mode: 26
Symbol slip mode: 27
28 UG028, July 1, 2014 28
EFIFO Operation 29
30 UG028, July 1, 2014 30
8b/10b Decoder 31
Bit Slider 31
PCS Self Test Checker 32
PCS Interface 33
PIPE Interface 34
Clocking 36
Debug and Test 38
PMA loopback modes: 39
PCS loopback modes: 39
PMA Test Pattern Generator 40
PMA Test Pattern Checker 40
PCS Test Pattern Generator 40
PRBS Generator 40
PCS Test Pattern Checker 41
Latency 42
44 UG028, July 1, 2014 44
Configurations Supported 45
46 UG028, July 1, 2014 46
48 UG028, July 1, 2014 48
Single-Lane Serdes Wrapper 50
52 UG028, July 1, 2014 52
Overview Section: 53
Entry field 54
Purpose 54
Available Options 54
Choice made 54
56 UG028, July 1, 2014 56
Section on PMA Settings: 57
58 UG028, July 1, 2014 58
RX PMA Equalization 59
RX PMA PLL 60
TX PMA Driver 62
TX PMA PLL 62
Section on PCS Settings: 63
RX PCS Settings 64
RX PCS Symbol Alignment 66
TX PCS Settings 68
70 UG028, July 1, 2014 70
Files Generated by ACE-GUI 71
Design and Wrapper Files 72
Sequence 74
76 UG028, July 1, 2014 76
Placement of SerDes 77
Timing Constraints 78
Design Guidelines 80
Figure 37: Clock Region View 82
84 UG028, July 1, 2014 84
Wide Bus 86
Design Tips 87
88 UG028, July 1, 2014 88
90 UG028, July 1, 2014 90
92 UG028, July 1, 2014 92
Design Bypassing PCS: 93
Modification – 1 (ACE GUI): 94
96 UG028, July 1, 2014 96
ACX_SERDES_SBUS_IF Module 99
General signals: 100
SerDes signals: 100
Parallel Interface signals: 100
UG028, July 1, 2014 101
Pass-through signals: 102
Loopback Modes 102
SerDes signals 102
Control signals 102
SerDes Registers 103
Electrical Specifications 104
Transmitter 105
106 UG028, July 1, 2014 106
Receiver 108
Eye Diagram 110
Reference Clock 112
Revision History 113

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