Achronix Speedster22i SerDes Manual do Utilizador Página 60
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Entry field
Purpose
Available Options*
Choice made
High Freq AGC
AC Boost
Control AC boost of High
frequency AGC
32 options ranging from
0.4 dB to 18.3 dB
Min 0: Boost 0.7dB
Max 31: Boost 22.6dB
7.8 db (default)
DFE Pulse-
shaping Tap 3dB
Freq
3dB Frequency of Pulse-Shaped
Analog
Decision Feedback Equalizer
used to
deal with channel loss
• 105 MHz
• 179 MHz
• 281 MHz
• 391 MHz
• 494 MHz
• 567 MHz
• 663 MHz
•
808 MHz
105 MHz
(default)
DFE Pulse-
shaping Tap
Gain
Tap gain of Pulse-Shaped
Analog
Decision Feedback Equalizer
used to
deal with channel loss
• No pulse shaping tap
• -0.38 dB
• -0.78 dB
• -1.20 dB
• -1.63 dB
• -2.09 dB
• -2.58 dB
•
-3.10 dB
No pulse
shaping tap
(default)
DFE N-1 Tap
Gain Control
(mV)
Additional DFE taps to
equalize channel discontinuities
-59.99 mV to +59.99 mV at
8.57 mV interval
0 (default)
DFE N-2 Tap
Gain Control
(mV)
Additional DFE taps to
equalize channel discontinuities
-49.98 mV to +49.98 mV at
7.14 mV interval
0 (default)
DFE N-3 Tap
Gain Control
(mV)
Additional DFE taps to
equalize channel discontinuities
-39.97 mV to +39.97 mV at
5.71 mV interval
0 (default)
DFE N-4 Tap
Gain Control
(mV)
Additional DFE taps to
equalize channel discontinuities
-29.96 mV to +29.96 mV at
4.28 mV interval
0 (default)
RX User Control
From Fabric
• True
*1
• False
False (default)
*1 If True is selected, the ACE GUI will add two input ports to the wrapper RTL. This change is
reflected in IP Diagram sub-window by the two additional ports: ch0_i_pma_RXeqlut[32:0] and
ch0_i_pma_RXeqlut_str.
* Available options listed here are the current ones based on characterization data. These values are
subject to change.
RX PMA PLL
This page allows the user to configure the PMA PLL settings on the receive path. The entry
fields and the available options are listed in “Table 14: RX PMA PLL Settings”. This table also
presents the choices that are made for the current design: simple_serdes_design.
60 UG028, July 1, 2014
- Speedster22i SerDes 1
- User Guide 1
- Table of Contents 2
- 4 UG028, July 1, 2014 4
- List of Figures 5
- List of Tables 6
- Overview 7
- Major standards supported 9
- 10 UG028, July 1, 2014 10
- SerDes Placement 11
- SerDes Architecture Overview 12
- 1. Common 13
- 3. Digital PMA (DPMA) 14
- PCS Self Test Logic 16
- 18 UG028, July 1, 2014 18
- Interface Encapsulation 20
- 8b/10b Encoder 20
- Running Disparity 20
- 22 UG028, July 1, 2014 22
- Polarity Bit Reversal (PBR) 23
- Symbol Alignment 23
- Modes of Operation 24
- Manual Mode: 24
- Bit Slip Mode: 24
- Automatic Mode: 24
- Deskew FIFO 25
- Functional Description 26
- Auto Mode: 26
- Symbol slip mode: 27
- 28 UG028, July 1, 2014 28
- EFIFO Operation 29
- 30 UG028, July 1, 2014 30
- 8b/10b Decoder 31
- Bit Slider 31
- PCS Self Test Checker 32
- PCS Interface 33
- PIPE Interface 34
- Clocking 36
- Debug and Test 38
- PMA loopback modes: 39
- PCS loopback modes: 39
- PMA Test Pattern Generator 40
- PMA Test Pattern Checker 40
- PCS Test Pattern Generator 40
- PRBS Generator 40
- PCS Test Pattern Checker 41
- Latency 42
- 44 UG028, July 1, 2014 44
- Configurations Supported 45
- 46 UG028, July 1, 2014 46
- 48 UG028, July 1, 2014 48
- Single-Lane Serdes Wrapper 50
- 52 UG028, July 1, 2014 52
- Overview Section: 53
- Entry field 54
- Purpose 54
- Available Options 54
- Choice made 54
- 56 UG028, July 1, 2014 56
- Section on PMA Settings: 57
- 58 UG028, July 1, 2014 58
- RX PMA Equalization 59
- RX PMA PLL 60
- TX PMA Driver 62
- TX PMA PLL 62
- Section on PCS Settings: 63
- RX PCS Settings 64
- RX PCS Symbol Alignment 66
- TX PCS Settings 68
- 70 UG028, July 1, 2014 70
- Files Generated by ACE-GUI 71
- Design and Wrapper Files 72
- Sequence 74
- 76 UG028, July 1, 2014 76
- Placement of SerDes 77
- Timing Constraints 78
- Design Guidelines 80
- Figure 37: Clock Region View 82
- 84 UG028, July 1, 2014 84
- Wide Bus 86
- Design Tips 87
- 88 UG028, July 1, 2014 88
- 90 UG028, July 1, 2014 90
- 92 UG028, July 1, 2014 92
- Design Bypassing PCS: 93
- Modification – 1 (ACE GUI): 94
- 96 UG028, July 1, 2014 96
- ACX_SERDES_SBUS_IF Module 99
- General signals: 100
- SerDes signals: 100
- Parallel Interface signals: 100
- UG028, July 1, 2014 101
- Pass-through signals: 102
- Loopback Modes 102
- SerDes signals 102
- Control signals 102
- SerDes Registers 103
- Electrical Specifications 104
- Transmitter 105
- 106 UG028, July 1, 2014 106
- Receiver 108
- Eye Diagram 110
- Reference Clock 112
- Revision History 113
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