Achronix Speedster22i User Macro Guide Manual do Utilizador Página 1

www.achronix.comSpeedster22i Macro Cell LibraryUG021 v1.7 – Oct 24, 2014

PAGE ix www.achronix.com Speedster Macro Cell LibraryBRAM80KECC ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Logic Functions MUX2Speedster Macro Cell Librarywww.achronix.com PAGE 83VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library

Speedster Macro Cell Library AchronixSemiconductorProprietary PAGE 84Chapter 4 – Lookup Table (LUT) FunctionsLUT4Four Input Lookup Tabledin0LUT4qdin

Lookup Table (LUT) Functions LUT4Speedster Macro Cell LibraryAchronixSemiconductorProprietary PAGE 85Table 4-3: Function Tabledin3 din2 din1 din0 q

Speedster Macro Cell Library www.achronix.com PAGE 86Chapter 5 – Arithmetic FunctionsALUTwo Input Adder / Subtractor with Programmable LoadALUa[1:0]b[

Arithmetic Functions ALUSpeedster Macro Cell Librarywww.achronix.com PAGE 87ParametersTable 5-2: Parameters Parameter Defined Values Default Valueinv

Arithmetic Functions ALUSpeedster Macro Cell Librarywww.achronix.com PAGE 88VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------libr

Speedster22i Macro Cell Library AchronixSemiconductorProprietary PAGE 89Chapter 6 – MemoriesBRAM80K80k-bit Dual-Port MemoryBRAM80Kaddrb[15:0]dinb[31

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 90BRAM80K PinsTable 6-1: BRAM80K Pin DescriptionsName Type Des

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 91ParametersTable 6-2: BRAM80K Parameters Parameter Defined Va

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 92porta_read_width(portb_read_width)The porta_read_width(portb

Speedster Macro Cell Library www.achronix.com PAGE xrst_sync_mode ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 93porta_reg_rstval(portb_reg_rstval)The porta_reg_rstval(portb

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 94porta_srval(portb_srval)The porta_srval(portb_srval) parame

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 95initpx_00 – initpx_31Theinitpx_00throughinitpx_31paramete

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 96Table 6-8: dina(dinb) bit assignments per porta_write_width(

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 97Table 6-10: douta(doutb) bit assignments per porta_read_widt

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 98Table 6-12: Mapping of Word Sizes to the Native 2048x40 Memo

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 99Table 6-13: BRAM Output Function Table for Latched Mode (Ass

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 100correctdataatbothoutputports.Inthiscase,thedatac

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 101Figure 6-5: No-Change, Latched Mode Timing DiagramFigure 6-

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 102When the BRAM80K memory is configured with port widt

PAGE xi www.achronix.com Speedster Macro Cell Libraryregce_priority_sub ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 103BRAM80K Verilog Instantiation TemplateBRAM80K #( .porta_re

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 104 .initd_019(256'h0), .initd_020(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 105 .initd_065(256'h0), .initd_066(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 106 .initd_111(256'h0), .initd_112(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 107 .initd_157(256'h0), .initd_158(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 108 .initd_203(256'h0), .initd_204(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 109 .initd_249(256'h0), .initd_250(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 110 .initpx_07(256'h0), .initpx_08(256'h0), .in

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 111 .rstregb(user_rstregb),

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 112 initd_007 => X"0000000000000000000000000000000

Speedster Macro Cell Library www.achronix.com PAGE xiiPLLControl ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 113 initd_062 => X"0000000000000000000000000000000

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 114 initd_117 => X"0000000000000000000000000000000

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 115 initd_172 => X"0000000000000000000000000000000

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 116 initd_227 => X"0000000000000000000000000000000

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 117 initp_26 => X"00000000000000000000000000000000

Memories BRAM80KSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 118 addrb => user_addrb , dinb => user_dinb ,

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 119BRAM80KFIFO80k-bit FIFO MemoryBRAM80KFIFOdout[31:0]doutp

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 120Table 6-15: BRAM80KFIFO Pin DescriptionName TypeClock D

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 121ParametersTable 6-16: BRAM80KFIFO Parameters Parameter

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 122Table 6-17: FIFO write_width versus Maximum Write Depth

PAGE xiii www.achronix.com Speedster Macro Cell Library

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 123Table 6-19: FIFO read_width versus Maximum Read Depthre

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 124Table 6-21: Valid Read Width Versus Write Width Combina

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 125reg_initvalThe reg_initval parameter defines the 40

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 126Table 6-25: Relationship of reg_srval bit positions to

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 127inputs.Alternatively, the user may also program

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 128Table 6-27: Reset Usage Model for wrrst and rdrst Input

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 129event when transferring the Write Pointer across

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 130rdrst_sync_stagesThe rdrst_sync_stages parameter defi

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 131rdcount_sync_modeThe rdcount_sync_mode parameter defi

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 132Table 6-34: Condition to Assert almost_empty Flag based

Speedster Macro Cell Library www.achronix.com PAGE xivPrefaceIntroductionThe Achronix Macro Cell Library provides the user with building blo

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 133Read and Write Count OutputsWrite Count OutputThe Write

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 134Status FlagsEmpty FlagTheEmpty(empty)flagisasserted

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 135Read Error FlagTheReadError(read_err)flagisasserte

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 136Flag Latency in Terms of Read Clock Cycles and

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 137FIFO Operational ModesTheFIFOmacrosupportsbothsingl

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 138FIFO may be configured with or without the outpu

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 139Figure 6-12: Basic Mode FIFO Reset Timing DiagramAdvanc

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 140Figure6‐9: Readand Write PointerResetInput Selec

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 141Figure 6-13: Reset Behavior Timing Diagram (Requires sy

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 142Writing an Empty Asynchronous FIFO (sync_mode = 1’b0)Fig

Cell Naming ConventionsSpeedster Macro Cell Librarywww.achronix.com PAGE xvCell Naming ConventionsRegister Naming ConventionsDFFNERResetR–Reset(has

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 143Writing to an Almost Full FIFO (en_wr_when_full = 1’b0)F

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 144Reading from an Almost Empty FIFO (en_rd_when_empty = 1’

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 145Reading from an Almost Empty FIFO (en_rd_when_empty = 1’

Memories BRAM80KFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 146Writing and Reading a Mixed-Width FIFOFigure 6-21: Writ

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 147BRAM80KECC80k-bit Simple Dual-Port Memory with Error Corr

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 148BRAM80KECC PinsTable 6-41: BRAM80KECC Pin DescriptionsNa

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 149en_out_regThe en_out_regparameter enables the regist

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 150decoder_enableThe decoder_enable parameter defines if

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 151BRAM80KECC Modes of OperationThere are three modes of

Memories BRAM80KECCSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 152Figure 6-24: ECC Write Operation Timing DiagramFigure 6-

Conventions Used in this GuideSpeedster Macro Cell Librarywww.achronix.com PAGE xviConventions Used in this GuideItem Format ExamplesCommand-line entr

Memories BRAM80KECCFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 153BRAM80KECCFIFO80k-bit FIFO Memory with Error Correcti

Memories BRAM80KECCFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 154Table 6-46: BRAM80KECCFIFO Pin DescriptionName TypeC

Memories BRAM80KECCFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 155ParametersTable 6-47: BRAM80KECCFIFO Parameters Para

Memories LRAM640Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 156LRAM640640-bit (64x10) Simple-Dual-Port MemoryLRAM640rdaddr[

Memories LRAM640Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 157LRAM640 PinsTable 6-48: LRAM640 Pin DescriptionsName Type D

Memories LRAM640Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 158write_clock_polarityThewrite_clock_polarityparameterisus

Memories LRAM640Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 159Simultaneous Memory OperationsMemory operations may be p

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 160LRAMFIFOLRAM-Based 64-Word FIFO MemoryLRAMFIFOdout[width -

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 161Table 6-50: LRAMFIFO Pin DescriptionName TypeClock DomainD

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 162ptr_sync_modeThe ptr_sync_mode parameter is used to b

Table 1-1: Supported Single-Ended Voltage Standards I/O Standard ParameterOutput VDDO (Volts)Input VDDI(Volts)VREF (Volts)(1)DescriptionHSTL15_I 1.5

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 163transferringtheReadPointeracrossclockdomains.Asane

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 164Figure 6-35: Write Pointer Reset Input Selection Block Dia

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 165Table 6-56: Condition to Assert almost_full Flag based on

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 166ofblindwritestotheFIFOthatcanbemadewithoutmonito

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 167Forexample,the emptyflagiscomputedfromtheSynchroni

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 168Synchronous FIFO Mode (ptr_sync_mode = 1’b1)Thesynchronous

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 169Writing an Empty Asynchronous FIFO (ptr_sync_mode = 1’b0)Fi

Memories LRAMFIFOSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 170Writing to an Almost Full FIFOFigure 6-40: Writing to an A

Speedster22i Macro Cell Library AchronixSemiconductorProprietary PAGE 171Chapter 7 – MultipliersBMACC5628 x 28 Multiplier / Accumulatora[27:0]ce_ars

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 172qcedr56561cascade_in[55:0]qcedrqcedrqcedrqcedr2828a[27:0

I/O Cells IOPADSpeedster Macro Cell Librarywww.achronix.com PAGE 2IOPADBidirectional I/O PaddindoutpadoeIOPADFigure 1-1: IOPAD Logic SymbolIOPADisa

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 173BMACC56 PinsTable 7-2: BMACC56 Pin DescriptionName Type

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 174rst_b inputData Input B Register Reset (active-low). Asse

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 175ParametersTable 7-3: BMACC56 Parameters Parameter Define

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 176init_aTheinit_aparameterdefinesthepower‐updefaultv

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 177rst_value_mask_addaThe rst_value_mask_adda parameter d

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 178regce_priority_doutThe regce_priority_dout parameter d

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 179sel_cinThe sel_cin parameter defines what  is route

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 180BMACC56 Verilog Instantiation TemplateBMACC56 #( .init_

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 181 .ce_mask_adda(user_ce_mask_adda), .ce_dout(user_ce

Multipliers BMACC56Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 182 reg_addb => ‘0’; reg_mask

Speedster22i Macro Cell Library www.achronix.com PAGE iCopyright InfoCopyright © 20 06– 20 13 Achronix Semiconductor Corporation. All rights r

I/O Cells IOPADSpeedster Macro Cell Librarywww.achronix.com PAGE 3Verilog Instantiation TemplateIOPAD #(.location(""), .iostandard("

Multipliers BMULT28X28Speedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 183BMULT28X2828  28 Signed Multiplierdin0[27:0]din1[27:0

Speedster Macro Cell Library www.achronix.com PAGE 184Chapter 8 – Special FunctionsACX_DESERIALIZE (Speedster22iHP Only)1:N Serial-to-Parallel Convert

Special Functions ACX_DESERIALIZE (Speedster22iHP Only)Speedster Macro Cell Librarywww.achronix.com PAGE 185VHDL Instantiation Template------------- A

Special Functions ACX_SERIALIZE (Speedster22iHP Only)Speedster Macro Cell Librarywww.achronix.com PAGE 186ACX_SERIALIZE (Speedster22iHP Only)N:1 Paral

Special Functions ACX_SERIALIZE (Speedster22iHP Only)Speedster Macro Cell Librarywww.achronix.com PAGE 187library speedster22i;use speedster22i.compon

Speedster Macro Cell Library www.achronix.com PAGE 188Chapter 9 – PLL/DLL Clock GeneratorsACX_CLKGENPhase-Locked Loop Clock GeneratorACX_CLKGENrefclkf

Table 9-1: Ports Name Type DescriptionrefclkReference Clock. The reference clock, which is optionally divided by the Reference Divider, is fed into t

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 190ParametersTable 9-2: ParametersParameter Description Defined

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 191bypass2 Clkout[2] Bypass.0: clkout[2] driven by PLL output.1:

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 192dyn_phase1 Clkout[1] Dynamic Phase Shift Select. If en_phase1

I/O Cells IOPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 4IOPAD_DBidirectional Registered I/O Pad with Asynchronous or Synchronous Set/Reset

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 193high_cnt2 The output synthesizer divides the PLL output clock

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 194Figure 9-2: ACX_CLKGEN Block DiagramACX_CLKGEN ComponentsRefe

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 195However,outputcyclesotherthan 50%arenotsupportedatth

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 196Mixed Feedback ModeMixed Feedback mode should only be us

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 197Figure 9-3: Serial Control Bus Read OperationFigure 9-4: Ser

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 198CSR_ADDR_SYNTHOUT1 8’h02 0 in/out outdiv1[0] Clkout[1] Output

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 199CSR_ADDR_SYNTHOUT_BYPASS_RST8’h07 0 in/out bypass0 Bypass Clko

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 200CSR_ADDR_SYNTHSSCMODGAIN_LSB8’h0B 0 in/out frac_div_ctrl[0] Fe

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 201CSR_ADDR_DFTADDR 8’h10 0 in/out Reserved Reserved1 in/out Rese

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 202CSR_ADDR_LDO_CTL 8’h15 0 in/out Reserved Reserved1 in/out Rese

Table 1-7: Ports Name Type Descriptionpad Bidirectional device pad.dinPositive-edge based data input. If parameter txregmode=”reg”, data is clocked i

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 203Verilog Instantiation Template ACX_CLKGEN # ( .clkdiv

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 204 .low_cnt0 (10'h0), .half_cycle0 (1&ap

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 205VHDL Instantiation Template------------- ACHRONIX LIBRARY ----

PLL/DLL Clock Generators ACX_CLKGENSpeedster Macro Cell Librarywww.achronix.com PAGE 206 dyn_phase3 => "0", byp_clkdiv3 => "

Speedster Macro Cell Library www.achronix.com PAGE 207Revision HistoryThefollowingtableliststhe revisionhistoryofthisdocument.Version Revisio

I/O Cells IOPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 6Table 1-8: ParametersParameter Defined Values Default Valuelocationiostandard “LV

I/O Cells IOPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 7Verilog Instantiation TemplateIOPAD_D #(.location(""), .iostandard(

I/O Cells IOPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 8-- Component InstantiationIOPAD_D_instance_name : IOPAD_D generic map (location =

I/O Cells IOPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 9IOPAD_D2Bidirectional DDR I/O Pad with Asynchronous or Synchronous Set/Resetqcedr

I/O Cells IOPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 10Table 1-12: Ports Name Type Descriptionpad inout Bidirectional device pad.dina

I/O Cells IOPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 11Table 1-13: ParametersParameter Defined Values Default Valuelocationiostandard

I/O Cells IOPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 12Verilog Instantiation TemplateIOPAD_D2 #(.location(""), .iostanda

Speedster Macro Cell Library www.achronix.com PAGE iiTable of ContentsPreface ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

I/O Cells IPADSpeedster Macro Cell Librarywww.achronix.com PAGE 13IPADNon-Registered Input PaddoutpadIPADFigure 1-6: IPAD Logic SymbolIPADisanasyn

I/O Cells IPADSpeedster Macro Cell Librarywww.achronix.com PAGE 14VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library speeds

I/O Cells IPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 15IPAD_DRegistered Input Pad with Asynchronous or Synchronous Set/Resetqcedrstndoutp

I/O Cells IPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 16Table 1-19: Input Function tablepad rxdata_en rxclk doutVerilog Instantiation Tem

I/O Cells IPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 17IPAD_D2DDR Input Pad with Asynchronous or Synchronous Set/ResetdoutapadIPAD_D2qdr

I/O Cells IPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 18Table 1-21: ParametersParameter Defined Values Default Valuelocationiostandard “

I/O Cells IPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 19 keepmode => "none", hysteresis => &q

I/O Cells IPAD_DIFFSpeedster Macro Cell Librarywww.achronix.com PAGE 20IPAD_DIFFNon-Registered Differential Input PaddoutpadIPAD_DIFFpadnFigure 1-10:

I/O Cells IPAD_DIFFSpeedster Macro Cell Librarywww.achronix.com PAGE 21Verilog Instantiation TemplateIPAD_DIFF #(.locationp(""), .loca

I/O Cells IPAD_DIFFDSpeedster Macro Cell Librarywww.achronix.com PAGE 22IPAD_DIFFDRegistered Differential Input Pad with Asynchronous or Synchronous S

PAGE iii www.achronix.com Speedster Macro Cell LibraryRegisteredDifferentialInputPadwithAsynchronousorSynchronousSet/Reset‐‐‐‐‐‐‐‐‐‐

I/O Cells IPAD_DIFFDSpeedster Macro Cell Librarywww.achronix.com PAGE 23Table 1-27: Input Function tablepad padn rxdata_en rxclk doutVerilog Instanti

I/O Cells IPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 24IPAD_DIFFD2DDR Differential Input Pad with Asynchronous or Synchronous Set/Re

I/O Cells IPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 25Table 1-29: ParametersParameter Defined Values Default Valuelocationplocatio

I/O Cells IPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 26 generic map (location => ““, iostandard => “LVCMOS18”,

I/O Cells OPADSpeedster Macro Cell Librarywww.achronix.com PAGE 27OPADNon-Registered Output Paddin padOPADFigure 1-14: OPAD Logic SymbolOPADisanno

I/O Cells OPADSpeedster Macro Cell Librarywww.achronix.com PAGE 28VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library speeds

I/O Cells OPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 29OPAD_DRegistered Output Pad with Asynchronous or Synchronous Set/Resetqcedrstnrstn

I/O Cells OPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 30Table 1-34: ParametersParameter Defined Values Default Valuelocationiostandard “L

I/O Cells OPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 31VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library spee

I/O Cells OPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 32OPAD_D2DDR Output Pad with Asynchronous or Synchronous Set/ResetqcedrstnpadOPAD_D

Speedster Macro Cell Library www.achronix.com PAGE ivPins ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

I/O Cells OPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 33Table 1-38: ParametersParameter Defined Values Default Valuelocationiostandard “

I/O Cells OPAD_D2Speedster Macro Cell Librarywww.achronix.com PAGE 34VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library spe

I/O Cells OPAD_DIFFSpeedster Macro Cell Librarywww.achronix.com PAGE 35OPAD_DIFFNon-Registered Differential Output PaddinpadOPAD_DIFFpadnFigure 1-18:

I/O Cells OPAD_DIFFSpeedster Macro Cell Librarywww.achronix.com PAGE 36 instance_name (.din(user_din), .pad(user_pad), .padn(user_padn

I/O Cells OPAD_DIFFDSpeedster Macro Cell Librarywww.achronix.com PAGE 37OPAD_DIFFDRegistered Differential Output Pad with Asynchronous or Synchro-nous

I/O Cells OPAD_DIFFDSpeedster Macro Cell Librarywww.achronix.com PAGE 38Table 1-43: ParametersParameter Defined Values Default Valuelocationplocation

I/O Cells OPAD_DIFFDSpeedster Macro Cell Librarywww.achronix.com PAGE 39VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library

I/O Cells OPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 40OPAD_DIFFD2DDR Differenctial Output Pad with Asynchronous or Synchronous Set/

I/O Cells OPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 41Table 1-47: ParametersParameter Defined Values Default Valuelocationplocatio

I/O Cells OPAD_DIFFD2Speedster Macro Cell Librarywww.achronix.com PAGE 42VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library

PAGE v www.achronix.com Speedster Macro Cell LibraryDFFN ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

I/O Cells TPADSpeedster Macro Cell Librarywww.achronix.com PAGE 43TPADNon-Registered Tristate Output Paddin padTPADoeFigure 1-22: TPAD Logic SymbolTP

I/O Cells TPADSpeedster Macro Cell Librarywww.achronix.com PAGE 44VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library speeds

I/O Cells TPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 45TPAD_DRegistered Tristate Output Pad with Asynchronous or Synchronous Set/Resetqce

I/O Cells TPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 46Table 1-52: ParametersParameter Defined Values Default Valuelocationiostandard “L

I/O Cells TPAD_DSpeedster Macro Cell Librarywww.achronix.com PAGE 47VHDL Instantiation Template------------- ACHRONIX LIBRARY ------------library spee

Speedster22i Macro Cell Library AchronixSemiconductorProprietary PAGE 49Chapter 2 – RegistersNaming ConventionTheseMacrosarenamedbaseduponthei

Registers DFFSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 50ParametersTable 2-2: Parameters Parameter Defined Values Defaul

Registers DFFESpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 51DFFEPositive Clock Edge D-Type Register with Clock EnablecedckD

Registers DFFESpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 52Verilog Instantiation TemplateDFFE #(.init(1’b0)) instance_nam

Registers DFFECSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 53DFFECPositive Clock Edge D-Type Register with Clock Enable and

Speedster Macro Cell Library www.achronix.com PAGE viinit‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Registers DFFECSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 54Table 2-9: Function TableInputs Outputcn ce d ck qVerilog

Registers DFFEPSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 55DFFEPPositive Clock Edge D-Type Register with Clock Enable and

Registers DFFEPSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 56Table 2-12: Function TableInputs Outputpn ce d ck qVerilog

Registers DFFERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 57DFFERPositive Clock Edge D-Type Register with Clock Enable and

Registers DFFERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 58sr_assertionThe sr_assertion parameter defines the behavi

Registers DFFERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 59VHDL Instantiation Template------------- ACHRONIX LIBRARY ----

Registers DFFESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 60DFFESPositive Clock Edge D-Type Register with Clock Enable and

Registers DFFESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 61sr_assertionThe sr_assertion param eter defines the behav

Registers DFFESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 62VHDL Instantiation Template------------- ACHRONIX LIBRARY ----

Registers DFFNSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 63DFFNNegative Clock Edge D-Type RegisterdcknDFFNqFigure 2-7: Lo

PAGE vii www.achronix.com Speedster Macro Cell LibraryTwoInputAdder/SubtractorwithProgrammableLoad ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Registers DFFNSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 64Verilog Instantiation TemplateDFFN #(.init(1’b0)) instance_nam

Registers DFFNECSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 65DFFNECNegative Clock Edge D-Type Register with Clock Enable a

Registers DFFNECSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 66Table 2-26: Function TableInputs Outputcn ce d ckn qVeril

Registers DFFNEPSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 67DFFNEPNegative Clock Edge D-Type Register with Clock Enable a

Registers DFFNEPSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 68Table 2-29: Function TableInputs Outputpn ce d ckn qVeril

Registers DFFNERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 69DFFNERNegative Clock Edge D-Type Register with Clock Enable a

Registers DFFNERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 70sr_assertionThe sr_assertion parameter defines the behav

Registers DFFNERSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 71VHDL Instantiation Template------------- ACHRONIX LIBRARY ---

Registers DFFNESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 72DFFNESNegative Clock Edge D-Type Register with Clock Enable a

Registers DFFNESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 73sr_assertionThe sr_assertion param eter defines the beha

Speedster Macro Cell Library www.achronix.com PAGE viiien_out_reg‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐

Registers DFFNESSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 74VHDL Instantiation Template------------- ACHRONIX LIBRARY ---

Registers DFFNRSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 75DFFNRNegative Clock Edge D-Type Register with Asynchronous Res

Registers DFFNRSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 76Table 2-40: Function TableInputs Outputrn d ckn q when sr_a

Registers DFFNSSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 77DFFNSNegative Clock Edge D-Type Register with Asynchronous Se

Registers DFFNSSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 78Table 2-44: Function TableInputs Outputsn d ckn q when sr_a

Registers DFFRSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 79DFFRPositive Clock Edge D-Type Register with Asynchronous Reset

Registers DFFRSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 80Table 2-48: Function Table when sr_assertion = “unclockedInput

Registers DFFSSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 81DFFSPositive Clock Edge D-Type Register with Asynchronous Sets

Registers DFFSSpeedster22i Macro Cell LibraryAchronixSemiconductorProprietary PAGE 82Table 2-52: Function TableInputs Outputsn d ck q when sr_ass

Speedster Macro Cell Library www.achronix.com PAGE 82Chapter 3 – Logic FunctionsMUX2Two Input Multiplexer Gatedin0MUX2doutdin1selFigure 3-1: Logic Sy