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Registers DFFES

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 61

sr_assertion

The sr_assertion param eter defines the behavior of the output when the sn set input is

asserted.Assigningthesr_assertionto“unclocked”resultsinanasychronousassertionofthe

reset signal, where the q output is set to one upon assertion of the active‐low reset signal.

Assigningthesr_assertionto“clocked”re

sultsinasynchronousassertionoftheresetsignal,

wheretheqoutputissettooneatthenextrisingedgeoftheclock.Thedefaultvalueofthe

sr_assertionparameteris“unclocked”.

Table 2-19: DFFES Function Table when sr_assertion = “unclocked”

Inputs Output

sn ce d ck q



Table 2-20: DFFES Function Table when sr_assertion = “clocked”

Inputs Output

sn ce d ck q



Verilog Instantiation Template

DFFES #(.init(1’b1),

.sr_assertion(“unclocked”))

instance_name

(.q(user_out),

.d(user_din),

.sn(user_set),

.ce(user_clock_enable),

.ck(user_clock));

0X X X 1

10 X XHold

11 0 0

1 1

0X X  1

X XHold

11 0 0

1 1

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 223 224

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