Achronix Speedster22i User Macro Guide Manual do Utilizador descarregar pdf (Página 98)

Registers DFFS

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 82

Table 2-52: Function Table

Inputs Output

sn d ck q



when sr_assertion = “unclocked’

Table 2-53: Function Table

Inputs Output

sn d ck q



when sr_assertion = “clocked’

Verilog Instantiation Template

DFFS #(.init(1’b1))

instance_name

(.q(user_out),

.d(user_din),

.sn(user_set),

.ck(user_clock));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

DFFS_instance_name : DFFS

generic map (

init => ‘1’)

port map (q => user_out,

d => user_din,

sn => user_set,

ck => user_clock);

0X  1

1X XHold

10 0

11 1

0X X 1

XHold

10 0

11 1

1 2 ... 93 94 95 96 97 98 99 100 101 102 103 ... 223 224

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Achronix Speedster22i User Macro Guide Manual do Utilizador Página 98