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Registers DFFNEC

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 65

DFFNEC

Negative Clock Edge D-Type Register with Clock Enable and

Synchronous Clear

ckn

DFFNEC

Figure 2-8: Logic Symbol

DFFNEC is a si

ngle D‐type register with data input (d), clock enable (ce) , clock (ckn), and

active‐low synchronous clear (cn) inputs and data (q) output. The active‐low synchronous

clearinputsetsthedataoutputlowuponthenextfallingedgeoftheclockifitisassertedlow

andtheclockenablesi

gnalisassertedhigh.Ifthesynchronous clearinputisnotasserted,the

dataoutputissettothevalueonthedatainputuponthenextfallingedgeoftheclockifthe

active‐highclockenableinputisasserted.

Pins

Table 2-24: Pin Descriptions

Name Type Description

d Data input.

Active-low synchronous clear input. A low

on cn sets the q output low

upon the next falling edge of the clock if the clock enable is asserted high.

ce Active-high clock enable input.

ckn Negative-edge clock input.

Data output. T

he value present on the data input is transferred to the q out-

put upon the falling edge of the clock if the clock enable input is high and

e synchronous clear input is high.

Parameters

Table 2-25: Parameters

Parameter Defined Values Default Value

init 1’b0

init

TheinitparameterdefinestheinitialvalueoftheoutputoftheDFFNECregister.Thisisthe

valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue

oftheinitparameteris1’b0.

input

output

1’b0, 1’b1

1 2 ... 76 77 78 79 80 81 82 83 84 85 86 ... 223 224

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