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Achronix Speedster22i User Macro Guide Manual do Utilizador Página 147

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Memories BRAM80KFIFO
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 130
rdrst_sync_stages
The rdrst_sync_stages parameter defines the number of stages of registers used to
synchronize the rdrst input pin to the wrclk clock domain if the rdrst signal is used by the
Write Pointer Reset. The value of the rdrst_sync_stages parameter is only used if the
wrrst_input_modeissetto2’b10or2’b11.Themappingoftherdrst_sync_stagesparameter
va
lue to the number of sychronization stages is defined in Table 6‐31
: Mapping
rdrst_sync_stages Parameter Se
ttings to Synchronization Stage Depth, where each stage
corresponds to a re
gister in the Read Reset Synchronizer shown in Figure 6‐9: Read and
WritePo
interResetInputSelectionBlockDiagram.For example,settingrdrst_sync_stages
to2’
b00configurestherdrstsynchronizationcircuittohavetwoback‐to‐backregistersinthe
WriteResetSynchronizer.Thedefaultvalueoftherdrst_sync_stagesparameteris2’b00.
Table 6-31: Mapping rdrst_sync_stages Parameter Settings to S
ynchronization Stage Depth
rdrst_sync_stages Read Reset Synchronization Stage Depth
2’b00 2
2’b01 3
2’b10 4
2’b11 5
rdptr_sync_stages
The rdptr_sync_stages parameter defines the number of stages used in the Read Pointer
SynchonizercircuitthatsynchronizestheReadPointertothewrclkclockdomain.Whenthe
FIFO is in asynchronous mode, (sync_mode = 1’b0), the output of the synchonized Read
Pointer is compared to the Write Pointer to generate the fu
ll and almost_full flags.The
synchronizedReadPointermayalsoberoutedtotherdcounteroutput(rdcount_sync_mode=
1’b0).Themappingoftherdptr_sync_stagesparametervaluetothenumberofsychronization
stagesisdefinedinTable6‐32
: Mappingrdptr_sync_stagesParameterSettingstoSynchro‐
nization Stage De
pth, where each stage corresponds to a register in the Read Pointer
Synchronizer circuit shown in Figure 6‐11
: Read Pointer Synchronizer Block Diagram.
Higher va
lues forthe rdptr_sync_stages parameter reduce the possibility of a metastable
event when transferring the Read Pointer across clock domains. As an example, setting
rdptr_sync_stages to 2’b00 configures the read pointer synchronization circuit to have two
back‐to‐back registers in the Read Pointer Synchonizer.The default value of the
rdptr_sync_stagesparameteris2’
b00.
Table 6-32: Mapping rdptr_sync_stages Parameter Settings to S
ynchronization Stage Depth
rdptr_sync_stages Read Pointer Synchronization Stage Depth
2’b00 2
2’b01 3
2’b10 4
2’b11 5
wrcount_sync_mode
The wrcount_sync_mode parameter defines whether the write counter (wrcount) output is
synchonous to the wrclk clock input. Assigning a value of 1’b0 to wrcount_sync_mode
configuresthewrcountoutputtobe synchonizedtotherdclkclock.Assigningavalueof1’b1
towrcount_sync_modeconfiguresthewrcountoutputtobesynchonizedtothewrcl
kclock.
Thedefaultvalueofthewrcount_sync_modeparameteris1’b1.
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