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Registers DFFNEP

Speedster22i Macro Cell Library

AchronixSemiconductorProprietary PAGE 67

DFFNEP

Negative Clock Edge D-Type Register with Clock Enable and

Synchronous Preset

ckn

DFFNEP

Figure 2-9: Logic Symbol

DFFNEP is a si

ngle D‐type register with  data  inpu t (d), clock enable (ce), clock  (ckn), and

active‐lowsynchronous preset (pn) inputs and data (q) output. The active‐lowsynchronous

presetinputsetsthe dataoutputhighuponthenextfallingedgeoftheclockifitisasserted

low and the clock enable si

gnal is asserted high. If the synchronous preset input is not

asserted,thedataoutputissettothevalueonthedatainputuponthenextfallingedgeofthe

clockiftheactive‐highclockenableinpu tisasserted.

Pins

Table 2-27: Pin Descriptions

Name Type Description

d Data input.

Active-low synchronous preset input.

A low on pn sets the q output high

upon the next falling edge of the clock if the clock enable is asserted high.

ce Active-high clock enable input.

ckn Negative-edge clock input.

Data output. T

he value present on the data input is transferred to the q out-

put upon the falling edge of the clock if the clock enable input is high and

the

synchronous preset input is high.

Parameters

Table 2-28: Parameters

Parameter Defined Values Default Value

init 1’b1

init

Theinitparameterde finestheinitialvalueoftheoutputoftheDFFNEPregister.Thisisthe

valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue

oftheinitparameteris1’b1.

input

output

1’b0, 1’b1

1 2 ... 78 79 80 81 82 83 84 85 86 87 88 ... 223 224

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