
Registers DFF
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 50
Parameters
Table 2-2: Parameters
Parameter Defined Values Default Value
init 1’b0
init
TheinitparameterdefinestheinitialvalueoftheoutputoftheDFFregister.Thisisthevalue
theregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalueofthe
initparameteris1’b0.
Table 2-3: Function Table
Inputs
Output
d ck q
Verilog Instantiation Template
DFF #(.init(1’b0))
instance_name
(.q(user_out),
.d(user_din),
.ck(user_clock));
VHDL Instantiation Template
------------- ACHRONIX LIBRARY ------------
library speedster22i;
use speedster22i.components.all;
------------- DONE ACHRONIX LIBRARY ---------
-- Component Instantiation
DFF_instance_name : DFF
generic map ( init => ‘0’)
port map (q => user_out,
d => user_din,
ck => user_clock);
1’b0, 1’b1
0 0
1 1
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