Achronix Speedster22i User Macro Guide Manual do Utilizador Página 85

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Registers DFFNER
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 69
DFFNER
Negative Clock Edge D-Type Register with Clock Enable and
Asynchronous/Synchronous Reset
rn
ce
d
ckn
DFFNER
q
Figure 2-10: Logic Symbol
DFFNER is a si
ngle Dtype register with data input (d), clock enable (ce), clock (ckn), and
activelowreset(rn)inputsanddata(q) output.Theactivelowresetinputoverridesallother
inputs when it is asserted low and sets the data output low. The resonseof the q output in
re
sponse to the asserted reset depends on the value of the sr_assertion parameter and is
detailedinTable232
: DFFNERFunctionTablewhensr_assertion=“unclocked”andTable
233: DFFNER Function Table wh
en sr_assertion = “clocked”. If the reset input is not
asserted,thedataoutputissettotheva
lueonthedatainputuponthenextfallingedgeofthe
clockiftheactivehighclockenableinpu tisasserted.
Pins
Table 2-30: Pin Descriptions
Name Type Description
d Data input.
rn
Active-low asynchronous/sy
nchronous reset input. A low on rn sets the
q output low independent of the other inputs if the sr_assertion parame-
ter is set to “unclocked”. If the sr_assertion parameter is set to “clocked”, a
lo
w on rn sets the q output low at the next falling edge of the clock.
ce Active-high clock enable input.
ckn Negative-edge clock input.
q
Data output. The value pr
esent on the data input is transferred to the q
output upon the falling edge of the clock if the clock enable input is high
and the reset input is high.
Parameters
Table 2-31: Parameters
Parameter Defined Values Default Value
init 1’b0
sr_assertion “unclocked
init
Theinitparameterdefinestheinitialvalueoftheoutput oftheDFFNERregister.Thisisthe
valuetheregistertakesupontheinitialapplicationofpowertotheFPGA.Thedefaultvalue
oftheinitparameteris1’b0.
input
input
input
input
output
1’b0, 1’b1
unclocked, “clocked”
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