Achronix Speedster22i User Macro Guide Manual do Utilizador descarregar pdf (Página 42)

I/O Cells IPAD_DIFFD2

Speedster Macro Cell Library

www.achronix.com PAGE 25

Table 1-29: Parameters

Parameter Defined Values Default Value

locationp

locationn

iostandard “LVCMOS18”

drive

rstmode

rstvalue

slew

keepmode

hysteresis

open_drain “true”, “false” “false”

pvt_comp “none”, “own” “none”

odt “off ”, “on” “off ”

termination “50”, “60”, “75”, “100”

, “120”, “240” “50”

Figure 1-13: IP

AD_DIFFD2 Input Timing Diagram (assumes data_en = 1’b1)

Verilog Instantiation Template

IPAD_DIFFD2 #(.locationp(""),

.locationn(""),

.iostandard("LVCMOS18"),

.drive("16"),

.rstmode("async"),

.rstvalue("low"),

.hysteresis("none"),

.pvt_comp("none"),

.termination("50"),

.odt("off"))

instance_name (.pad(user_pad), .padn(user_padn), .douta(user_douta),

.doutb(user_doutb), .d

ata_en(user_data_en), .txrstn(user_txrstn),

.rxrstn(user_rxrstn), .rstn(user_rstn), .clk(user_clk));

VHDL Instantiation Template

------------- ACHRONIX LIBRARY ------------

library speedster22i;

use speedster22i.components.all;

------------- DONE ACHRONIX LIBRARY ---------

-- Component Instantiation

IPAD_DIFFD2_instance_name : IPAD_DIFFD2

“<pad_location>” ““

“<padn_location>” ““

See Table1‐1

"2", "4", "6", "8", "12", "16" "16"

“sync”, “async” “async”

“low”, “high” “low”

“fast”, “slow” “slow”

"pullup", "pulldown", "none" “none”

"none", "schmitt" “none”

clk

douta

doutb

pad

padn

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 223 224

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