Achronix Speedster22i User Macro Guide Manual do Utilizador Página 146

  • Descarregar
  • Adicionar aos meus manuais
  • Imprimir
  • Página
    / 224
  • Índice
  • MARCADORES
  • Avaliado. / 5. Com base em avaliações de clientes
Vista de página 145
Memories BRAM80KFIFO
Speedster22i Macro Cell Library
AchronixSemiconductorProprietary PAGE 129
event when transferring the Write Pointer across clock domains. As an example, setting
wrptr_sync_stagesto 2’b00 configures the write pointer synchronization circuit to have two
backtoback registers in the Write Pointer Synchonizer.The default value of the
wrptr_sync_stagesparameteris2’b00.
Table 6-29: Mapping wrptr_sync_stages Parameter Settings to Synchronization Stage Depth
wrptr_sync_stages Write Pointer Synchronization Stage Depth
2’b00 2
2’b01 3
2’b10 4
2’b11 5
rdrst_rstval
The rdrst_rstval parameter defines the active level of the read port reset (rdrst ) input.
Assigningavalueof1’b0tordrst_rstvalconfiguresthereadportresetinputtohaveanactive
lowsynchronousreset,whileassigningavalueof1’b1configuresthereadportresetinpu tto
haveanactivehighsynchronousreset.Thedef
aultvalueofthewrrst_rstvalparameteris1’b1.
rdrst_input_mode
The rdrst_input_mode parameter defines how the Read Pointer is reset. The FIFO macro
providestheuserwithseveraloptionstoresettheFIFOeithersychronouslyortosynchronize
the reset input to the appropriate clock domain within the FIFO without the need to
implementseparatesynchronizationcircuitryintheFPGAfabric.
The Read Po
inter Reset input of the Read Pointer must be synchronous to the rdclk clock
domain.The user must either provide a synchronous reset via the wrrst or rdrst inpu ts or
synchronize the wrrst input.The method to reset the Read Pointer is selected via the
rdrst_input_mode paramter is defined in Table 630
: rdrst_input_mode Parameter
Mapping.
By configuring the wrrst_
input_mode and rdrst_input_mode parameters, the user may
choosetohavetheFIFOWritePointerandReadPointerresetbyoneorbothofthewrrst/rdrst
inputs.Alternatively, the user may also program the reset of the Write Pointer and Read
Pointer independently of each other.For example, the us
er may program the FIFO reset
inputstoactindependentlyofeachothersothattheReadPointerisresetexclusivelybythe
rdrst input to allow the contents of a previously written FIFO to be reread.Note that as a
result of the Read Pointer reset, the flag outputs are also updated. A block di
agram of the
ReadPointerResetselectioncircuitryisshowninFigure69: ReadandWritePo
interReset
Input S
election Block Diagram. The default value of the rdrst_input_mode parameter is
2’b10.
Table 6-30: rdrst_input_mode Parameter Mapping.
rdrst_input_mode
Selected Input for Read
Po
inter Reset
Read Pointer Reset Use Model
2’b00 rdrst input resets Read Pointer Requires rdrst input is synchronous to
rdclk clock domain
2’b01 wrrst input resets Read Pointer Requires wrrst input is synchronous to
r
dclk clock domain
2’b10 rdrst or synchronized wrrst
input r
esets Read Pointer
Read pointer may be reset by either
the synchronous rdrst or synchonized
wrrst inputs.
2’b11 Synchronized wrrst input resets
Re
ad Pointer
Read Pointer only reset by synchro-
nized wrrst input.
Vista de página 145
1 2 ... 141 142 143 144 145 146 147 148 149 150 151 ... 223 224

Comentários a estes Manuais

Sem comentários