wrclk
rdclk
wren
rden
din
dout (fwft = 1’b1)
empty (fwft = 1’b0)
almost_empty (fwft = 1’b0)
1. Almost Empty Offset programmed for 5 40-bit words (aempty_offset = 17’h00005)
Note: This timing diagram assumes:
2. wptr_sync_stages = 2’b00
3. sync_mode = 1’b0
wrd 0
wrd 1wrd 2wrd 3
dout (fwft = 1’b0)
wrd 0 wrd 1
wrd 0
wrd 4wrd 5wrd 6
A
AEvent : Begin writing 7 words to the FIFO.
Event : empty flag goes inactive one wrclk cycle plus (wrptr_sync_stages + 3) rdclk cycles for fwft = 1’b0.
after wren becomes active. The first word (wrd0) appears at the dout output if fwft = 1’b1.
B
B
4. In First Word Fall Through mode, the first word is guaranteed to be at the output no later than the cycle
when the empty flag transitions from the empty to thenon-empty state. Due to the asynchronous transfer
of the first written word from the write operation in the wrclk clock domain to the dout output in the rdclk
clock domain, word 0 may arrive at the dout output before the empty flag transitions from the empty to the
non-empty state.
C D
Previous Read Word
Previous Read Word
Event : almost_empty flag goes inactive one wrclk cycle plus (wrptr_sync_stages + 3) rdclk cycles
C
after wrd4 (6th word) is written into the FIFO (7th word if fwft = 1’b1).
D
Event : The second word (wrd1) appears at the dout output if fwft = 1’b1. The first (wrd0) appears
at the dout output if fwft - 1’b0.
empty (fwft = 1’b1)
empty flag goes inactive one wrclk cycle plus (wrptr_sync_stages + 4) rdclk cycles for fwft = 1’b1.
almost_empty (fwft = 1’b1)
wrclk
rdclk
wren
rden
din
dout
empty
almost_empty
1. Almost Empty Offset programmed for 5 40-bit words (aempty_offset = 17’h00006)
Note: This timing diagram assumes:
2. sync_mode = 1’b1
word 0 word 1 word 2 word 3
word 0
word 4 word 5
A
A
Event : Begin writing 6 words to the FIFO.
Event : empty flag goes inactive one wrclk cycle after wren becomes active.
B
B
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